arXiv:2611.09366v1 Announce Type: new Abstract: We present a decoding algorithm for a Reed--Solomon product code targeted at the demanding reliability requirements of modern magnetic tape storage. For a code $RS(256, 224)\times RS(175, 173)$ in a BSC we achieve post-decoding bit error rate (BER) of $10^{-20}$ at $\approx 5.3\times 10^{-3}$ raw BER while maintaining the common requirement to detect and correct 4 out of 32 dead tracks. We resolve two common problems of miscorrections and stall patterns that arise under such a high raw BER via simplified versions of anchor decoding and binary image analysis. The highest efficiency is achieved by performing an unlimited iterative decoder, which performs decoding iterations until no changes are made. We give an empirical analysis of the average number of iterations: below the raw BER of $5\times 10^{-3}$, four half-iterations are performed on average while improving substantially over a decoder that always performs 4 half-iterations. We provide a CPU implementation achieving 100-200 megabytes/s single-core throughput on a regular laptop and a design of a potential hybrid FPGA-CPU implementation of our decoder.