DeepSeek's 160,000 Huawei Ascend chips: what 10,000 chips for weeks actually buys, and why the reports disagree on training

TL;DR

Two reports about DeepSeek's planned Huawei Ascend 950DT cluster in Ulanqab, Inner Mongolia, point in different directions. Bloomberg's September 4 report, as summarized by secondary outlets, said the 160,000-chip deployment is for inference and that training stays on Nvidia. The Information's October 19 report said DeepSeek could start pre-training on the Ascend 950DT as soon as the end of 2026, and that a frontier run could need more than 10,000 Huawei chips working together for weeks. Aggregators recirculated the second claim on November 2 and 3.

I cannot settle which report is right. What I can do is check whether the second one is physically plausible. Using Huawei's published 950DT specification (1 PFLOPS FP8, 144 GB of memory at 4 TB/s) and DeepSeek's own published V3 numbers, 10,000 chips for about 13 days at 30% utilization delivers roughly the compute of the V3 pre-training run. That is a respectable mid-size run, not a frontier-scale one. The harder constraint is reliability: if the 950DT fails at the rate Meta reported for H100s during Llama 3 training, a 10,000-chip job takes about 5 unexpected interruptions per day.

The numbers below are my own arithmetic on public inputs. Where an input comes from a secondary source I say so, and the calculator at the end lets you change every assumption.

What has actually been reported about the Ulanqab cluster?

Here is the claim trail, with the weakest links marked. I have read the secondary summaries linked at the end, not the paywalled originals.

Two points matter for the rest of this post. First, the September and October reports are not strictly contradictory: a chip can be bought mostly for serving while a subset is used for an early pre-training run. Second, the hardware has not shipped in volume yet. One summary of the Bloomberg report also says Huawei's output is limited to the low hundreds of thousands of chips in 2026 because of memory supply, which would make full delivery a multi-year story.

What does the Ascend 950DT specification say?

Huawei's September 2025 roadmap lists the 950DT as the "decode and training" variant, due in the fourth quarter of 2026. The figures below are from that keynote.

Scaling these to the reported order gives a sense of size. 160,000 chips at 144 GB is 23.04 PB of HBM. At 1 PFLOPS FP8 each, the fleet's peak is 160 EFLOPS. A 10,000-chip training job, the figure from the October report, has 10 EFLOPS of peak FP8 and 1.44 PB of memory.

One caution on the cluster size. Dividing a 1 GW site by 160,000 chips gives 6.25 kW per accelerator. That is far more than a chip draws, so the site clearly includes cooling, networking, other tenants or headroom. Do not read it as a per-chip power figure.

How much pre-training compute is 10,000 chips for a few weeks?

The standard approximation for dense and mixture-of-experts training is FLOPs = 6 x N x D, where N is the number of parameters active per token and D is the number of training tokens. DeepSeek's V3 technical report gives 37 billion active parameters (671 billion total) and 14.8 trillion tokens, trained in 2.788 million H800 GPU-hours.

• 6 x 37e9 x 14.8e12 is about 3.3e24 FLOPs. The approximation ignores attention cost, so the true figure is a little higher.
• 3.3e24 FLOPs over 2.788 million GPU-hours works out to about 327 TFLOPS of useful throughput per H800. H100-class silicon, which has the same compute as the H800, peaks at roughly 1,979 TFLOPS dense FP8, so V3 ran at about 16% of peak by this accounting.

That second number is a useful anchor. A 950DT at 30% of its 1 PFLOPS peak delivers 300 TFLOPS, about the same useful throughput per chip that V3 got from H800s. So 30% is a reasonable, not heroic, planning assumption for a mature software stack, and 20% is a fair pessimistic case for a new one.

The chart shows how long 3.3e24 FLOPs takes at different cluster sizes and utilization levels.

At 10,000 chips and 30% utilization the answer is 12.7 days. At 20% it is 19 days. So "more than 10,000 chips for weeks" matches a V3-class run quite well. It does not match a frontier run. If the next model needs three times the V3 compute, the same 10,000 chips need 38 days; at ten times, 127 days.

This is where the full 160,000-chip fleet matters. At 30% utilization the whole fleet would finish a V3-class run in under a day, so a cluster that size is clearly sized for something other than one such run: serving, many parallel runs, or much larger training jobs once enough chips are online. That fits both reports at once, and it is a reason to be cautious about reading either one as the whole plan.

Does the memory fit?

Memory is not the binding constraint, which surprises people. With mixed-precision Adam training, a common rule of thumb is about 16 bytes of state per parameter: 2 for bf16 weights, 2 for gradients, 4 for fp32 master weights and 8 for the two Adam moments. DeepSeek's V3 recipe reduces some of this, but take 16 as an upper bound. On 10,000 chips with 1.44 PB of HBM, the state for even a 1-trillion-parameter model is 16 TB, about 1% of the memory. The rest is for activations, communication buffers and expert parallelism overhead.

What decides whether the run is efficient is bandwidth and software. A mixture-of-experts model spends a large share of each step in all-to-all communication between chips. The 950DT's 2 TB/s interconnect and the SuperPoD's all-optical fabric are designed for this, but there is no public training-scale measurement yet. Treat the 30% utilization above as an assumption to be tested, not a spec.

How often does a 10,000-chip job get interrupted?

Reliability is the part of the October report that deserves the most attention. The Llama 3 paper, which describes a 54-day snapshot of training on 16,384 H100 GPUs, reports 466 job interruptions, of which 419 were unexpected. That is one unexpected interruption roughly every 3.1 hours, with GPU and memory problems the largest category.

I scale that rate per chip, which is a strong assumption because Ascend failure rates are not public. The per-chip rate is 419 / 54 / 16,384, about 0.00047 interruptions per chip per day.

At 10,000 chips that is about 4.7 unexpected interruptions per day, or one every 5 hours, and around 95 in a 20-day run. At 40,000 chips it is one every 1.3 hours. Every interruption costs the time since the last checkpoint plus restart time, so checkpoint frequency and automatic recovery decide how much of the 30% utilization survives. Meta's own paper credits heavy automation for keeping effective training time above 90% despite this rate.

This is why the phrase "operating together for weeks" in the October report is a real milestone. Running a chip for weeks is easy. Keeping 10,000 of them in lockstep through hundreds of failures, on a new software stack, is the part nobody outside the project has seen demonstrated.

What should you take from this if you build or buy AI infrastructure?

1. Treat "will train on Huawei" and "will serve on Huawei" as separate questions. Serving needs memory capacity and bandwidth per chip; training needs interconnect, software maturity and failure handling. The 950DT is marketed for both, but the evidence for each is different.
2. Ask for utilization and goodput, not peak FLOPS. The V3 accounting above shows that a 1 PFLOPS chip and a 2 PFLOPS chip can deliver similar useful throughput once communication and software are counted.
3. Watch for the first shipped-hardware measurements. The signals that would change my view: a published training-throughput number from a real 950DT job, a reported interruption rate, or delivery volumes in Q4 2026 and Q1 2027.
4. Do not build a plan on unsourced ratios. The "four Ascend chips per GB300" figure circulating this week has no primary source. Even if true, the answer depends on precision, model and parallelism strategy.

Reproduce the numbers

# Days to reach a target compute budget on a cluster. All inputs are assumptions you can change. def days_to_train(flops_target, chips, peak_flops=1e15, mfu=0.30): return flops_target / (chips * peak_flops * mfu * 86400) v3 = 6 * 37e9 * 14.8e12 # about 3.29e24 FLOPs (6ND, attention ignored) for chips in (10_000, 20_000, 40_000): print(chips, [round(days_to_train(v3, chips, mfu=m), 1) for m in (0.2, 0.3, 0.4)]) # Interruptions: Llama 3 paper, 419 unexpected in 54 days on 16,384 GPUs rate = 419 / 54 / 16_384 # per chip per day for chips in (5_000, 10_000, 20_000, 40_000): print(chips, round(rate * chips, 2), "per day,", round(rate * chips * 20), "in 20 days") 

FAQ

Is DeepSeek really training on Huawei chips?
Not confirmed. The September Bloomberg report described inference use with training on Nvidia, and the October report from The Information described a possible pre-training start by the end of 2026. Neither company has confirmed the plan in the sources I could read.

How many chips does it take to match DeepSeek-V3's training compute?
About 3.3e24 FLOPs. At 1 PFLOPS FP8 peak and 30% utilization, 10,000 chips need roughly 13 days. Ten times the chips needs about 1.3 days, ignoring scaling losses.

What are the Ascend 950DT's specifications?
Huawei's roadmap lists 1 PFLOPS FP8, 2 PFLOPS MXFP4, 144 GB of memory at 4 TB/s and 2 TB/s of interconnect, with a Q4 2026 launch. These are vendor figures, not measurements from shipped hardware.

Why do large training runs fail so often?
At thousands of chips, even a low per-chip failure rate adds up. In Llama 3 training on 16,384 H100 GPUs, Meta reported 419 unexpected interruptions in 54 days, so recovery automation matters as much as peak speed.

Does 144 GB per chip limit model size?
Not at this cluster scale. With 10,000 chips the pooled memory is 1.44 PB, so training state for even a trillion-parameter model is a small share. Communication and software efficiency are the real limits.

Sources

• Bloomberg report of September 4, 2026, as summarized by AI Weekly
• The Information report of October 19, 2026, as summarized by AI Weekly and by ExplainX
• Aggregator article of November 2, 2026, used only to date the recirculation
• Huawei Connect 2025 keynote: Ascend 950 series and Atlas 950 SuperPoD specifications
• DeepSeek-V3 Technical Report: active parameters, tokens and GPU-hours
• The Llama 3 Herd of Models: training interruption statistics

Further reading

• Inference NPUs That Train: What a 325M Pretraining Run on a Rebellions ATOM-Max Shows, and What It Does Not
• Mistral Large 4 on your own GPUs: does 1 trillion parameters fit on 8 H200s, and what does the license allow?