arXiv:2611.07336v1 Announce Type: new Abstract: Within the Thompson VLSI model, the first energy optimal decoding schemes (up to polylogarithmic factors) that also reach clock cycle lower bounds are constructed. Let $N$ be block length. Then, there is an exponential error scaling function and a binary symmetric channel, such that for all $f(N)$ that scales to zero more slowly than this, there is a decoding scheme for this channel with error probability that scales as $O(f(N))$ that has number of clock cycles $T\le O(\sqrt{-\log(f(N)})\text{polylog}(N))$ and energy $E\le O(N\sqrt{-\log(f(N))}\text{polylog}(N))$. This matches fundamental lower bounds up to polylogarithmic factors. The technique uses expander-graph based LDPC codes, a mesh network architecture, and a parallelization technique. The key technical result needed for this is a lemma in graph theory. This lemma is used to show that communication graphs of bounded node degree can be routed through two- and three-dimensional mesh networks without overflowing the memory of any mesh node. Upper bounds are also extended to three dimensions.